This home work is based on all the material covered in the class, Lab in week 6, and Brown and Vranesic.
Each problem is worth 10 points each.
P1. Implement the two following functions at the same time
into the PLA in Figure 3.26 (p.89):
f1 = x1' x2'
x3' + x1' x2 x3' + x1' x2' x3 + x1 x2 x3
f2 = x1' x2'
x3' + x1 x2' x3' + x1' x2' x3 + x1 x2 x3
Note that the PLA has only 4 AND gates. So it can only generate 4 different
product terms. You may need to simplify the functions in order to incorporate
all the product terms into the PLA.
P2. Problem 3.2 in Brown and Vranesic.
P3. Problem 3.3 in Brown and Vranesic.
P4. Problem 3.49 in Brown and Vranesic.
P5. Problem 4.12 in Brown and Vranesic.
P6. Problem 4.32 in Brown and Vranesic.
P7. Problem 6.16 in Brown and Vranesic.
P8. Compute the worst case delay of a 1-bit ALU slice implementing add/sub, and, or, other functions and selection using a 4-1 bit mux (the one designed in class) in terms of t_fulladder (time of one bit full adder), t_2-1-mux (time for a 2 to 1 multiplexer), and t_4-1-mux (time for a 4 to 1 multiplexer).
P9. What are the worst case times for each function, i.e., ADD, SUB, AND, OR, and Other.
P10. Compute the worst case delay of a 4-bit ALU slice implementing add/sub, and, or, other functions and selection where adder is implemented using only two EXOR gates and carry bits are computed using a carry-look-ahead block you designed in Lab of week 4. The delay need to be computed in terms of t_gate (delay of a gate), t_CLA (time of 4 bit carry look ahead block), t_2-1-mux (time for a 2 to 1 multiplexer), and t_4-1-mux (time for a 4 to 1 multiplexer).