Introduction to Circuit Design in Quartus II
1. Objectives
In the previous lab you learned how digital circuits are simulated in Quartus II. You also learned how each circuit is related to a truth table and a logic expression. In this lab you will design two circuits and in the process, tackle one way of performing design entry: Schematic Capture. Other ways like the Truth Table and Verilog will be covered in future labs.
1.1 Reference Files
for Lab
2. Setup
As you did in previous labs, make sure you create the folder U:\CPRE281\Lab04a, and then two sub-folders \Lab04a\Lab04aStep1 and \Lab04a\Lab04aStep2. You will be saving your work and running your simulations in this lab from these two directories. This lab consists of two sections where you are asked to design a digital circuit in each.
2.1 Circuit 1
You will have to derive Truth Table, Logic Expression, and circuit diagram for the circuit described below.
NOTE: when a logic variable has a value of 1, we say that it is “asserted”.
Description:
You are
to construct a logic circuit with 
and
.
The logic is such that F is asserted only when A or B is asserted and C is not. First complete the truth table in the answer sheet, and then use it to construct a canonical sum-of-products (SOP) expression of the output F.
NOTE: before you start the simulation, verify with your lab instructor that you have the correct SOP expression.
You are now ready to build the circuit. Quartus II has logic gates and other basic logic functions available under the name of Primitives. For this step in the lab, you will learn how to use them to make your design in Schematic Capture. More information about Schematic Capture can be found in Appendix B.2 (page 751) of the Fundamentals of Digital Logic textbook.
You will need to create a new .qpf file and name it lab4aStep1.
To do this select File -> New Project Wizard…
Click the Next > button then make the following settings
Working directory: U:\CPRE281\Lab04a\Lab04aStep1
Name of project: Lab4aStep1
Name of top level design: Lab4aStep1
Then
click Finish.
NOTE: Since we will not be downloading this design, we do not need to select the MAX 7000S – EPM7128SLC84-7, and can simply leave these options as default.
Now you must create a new BDF file and add it to the project. To do this select File -> New. Under Device Design Files select Block Diagram/Schematic File.
Then select File -> Save As… set the file name to Lab4aStep1.bdf and make sure that the box for add file to current project is checked before saving.
You should now have a valid logic expression with AND, OR, and NOT gates. You will now start building the circuit, one logic gate at a time.
- Right click in the window and select Insert ->Symbol or double-click the in the window.
- In the Libraries menu select c:/altara/quartus42/libraries/ -> primitives -> logic. A list of gates will appear that you will need to create your project.
- Select the logic gate you want and hit the OK button. The gates are named by gate type and number of inputs to the gate, so a three-input AND gate is named and3 and so forth. Remember that your overall circuit should have three inputs and one output.
- Don’t forget to label the input and output pins with their respective variable names.
- Circuit elements can be moved around the design by clicking and dragging them. When you have the gates where you want them, you can wire them together with the Orthogonal Node Tool.
So far,
you have used the cursor as an arrow. This has allowed you to move around the
design, and move circuit elements. Clicking on the Orthogonal Node Tool,
the 
symbol of the left side tool bar will
change the cursor’s function. The Orthogonal Node Tool is used to connect
logic gates and other circuit elements together. You can also use the
Wiring Tool function by touching the cursor to the output or input of circuit
element and dragging to another element.
When you are done connecting your circuit, perform (Processing -> Compilation). You can now prepare your design for simulation. When you are done with the Vector Waveform Editor, you can then simulate your design and verify that it works correctly.
NOTE: Information about the Waveform Editor and the Simulator can be found in previous labs.
When you are done with your design, have the lab instructor verify it, and mark his/her initials in your answer sheet. Close all lab4aStep1 files in Quartus II.
2.2 Circuit 2
This is a classic
problem used to illustrate logic design. Again, you will need to create a new
.qpf file and name it lab4aStep2. Save this file under U:\CPRE281\Lab04a\Lab04aStep1, also create a new .bdf file
named Lab4aStep2.bdf and add it to the project.
Description:
A farmer owns two barns; one north of a creek and the other south. The farmer has a Cabbage, a Wolf, and a Goat. The Farmer needs to put each item in a barn every night. If the Cabbage and Goat are in the same barn, the Goat will eat the Cabbage. If the Wolf and the Goat are in the same barn, the Wolf will eat the Goat. The Farmer is worried and you have to design an alarm circuit that will let him know if two items can safely be placed in a barn.
For
this circuit, you have three 
and one
.
If an input is in the north barn, it gets assigned a logic 1, and if it is in the south barn it gets assigned a logic 0. The output Alarm, asserts if there are two items in a barn that cannot be kept together. Start by completing the truth table given in the answer sheet and use the truth table to construct a canonical sum-of-products (SOP) expression.
NOTE: before you start the simulation, verify with your lab instructor that you have the correct SOP expression.
Follow the same steps described in 2.1 and when you are finished, have your lab instructor verify your work and mark his initials in your answer sheet.
3. Complete
You are done with this lab. Please make sure you close all lab files, exit Quartus II, log off the computer, and hand in the lab answer sheet.