CPRE 381: Digital Systems,
Logic, Programming
Spring 2006
HW#10
Due Date: Wednesday, April 12
-
Write an exception handler for MPC555 to reside at address 0x500 with the
following behavior. It should check to see if the IRQ1 is the source of
interrupt. Both a mouse and a keyboard are connected to IRQ1. They each have
a control register with the least significant bit for ``READY'' and the next
bit for ``Interrupt Enable''. Your interrupt handler should prioritize mouse
over keyboard.
- Write an exception handler for Vector #5 that does not use SIVEC based
prioritization. It retains a history of servicing all of the possible 16
sources of interrupts in HISTORY[i]. When I0 (L0) is serviced,
HISTORY[0] (HISTORY[1]) is turned on. The exception handler
prioritizes (within software) by scanning all the sources of interrupt from
left to right in the order I0, L0, I1, L1, I2, L2, ..., I7, L7. The first
source that wants service and whose HISTORY[i] == 0 is serviced
(and HISTORY[i] is assigned 1). If a source i wants service,
but HISTORY[i] = 1, then it is serviced only if no other source
j with HISTORY[j] = 0 wants service. When all the sources have
been serviced, HISTORY[i] is forced to 0 for all i.
Service a Level k (IRQk) source by calling
Level-k-Handler (IRQ-k-Handler).