CPR E 381x/382x - Lab 1a
Register
File, ALU, and Shifter
1. Objectives
The purpose of the next few
labs is to construct a simple datapath.
This datapath will provide the functionality of a signed multiplier, as
well as supporting new features you will be studying in lecture. First, you will design some necessary components. Then these modules will be connected to form
the datapath. As class progresses, new
elements will be added to the datapath.
1.1 Reference Files for Lab
2. Prelab
Before you come to lab it
will be useful to review Register File, ALU, and shifter designs. In case you need to refer back, all lab
descriptions from last semester can be found here. You will also want to bring your textbook to
the lab as there are many helpful diagrams and schematics.
3. Setup
Create
a folder in your home directory U:\CPRE381\Lab01a,
and then three sub-folders ~\alu, ~\regfile, and ~\shifter. It is important that you use these
folder names. Each module should be in its own folder.
4. 32x32bit Registerfile in Verilog
In this part, you will design a register file, registerfile (datain, clock, regwrite, addrc, addra, addrb, port1,
port2)
that is capable of two simultaneous
register reads. Your registerfile should consist of 32 registers, each capable
of storing 32 bits. Thus, the input datain and the outputs port1 and port2 will be 32 bits wide.
The control signals addrc, addra, and addrb will be 5 bits wide each.
Your registerfile should write to the register specified by addrc on the negative edge of the clock if the regwrite signal is asserted.
The signals port1 and port2 will always display the data
contained in the registers addressed by addra
and addrb respectively.
To create your design, you should use the case
statement method as before. It will be
helpful to refer to your previous design, especially for creating a two
dimensional array.
Run a simulation using the vector waveform editor to
verify your design and check with the TA.
5. 32 bit ALU in Verilog
To construct a
32-bit ALU which performs ADD/SUB, AND, OR, and Set-on-Less-Than (SLT) operations, you need to first create a 1-bit
ALU. Each 1-bit ALU takes 1-bit a and 1-bit b input, a carryin
input and produces 1-bit g output, 1-bit p output, 1-bit result, and 1-bit sum. It also takes
3 control inputs,1-bit binv, and two bits op. The binv
input inverts the b input bit if asserted. There is an additional input called less
to support the SLT function, described in greater detail below. Here is a block diagram of the 1-bit alu:
The 2-bit input op
selects which of the four functions will be outputted to result. It selects ADD/SUB
of a and b when op is 00, AND of a and b when 01, OR of a and b when 10,
and SLT when 11. For the 1-bit ALU, the
SLT operation means result = less. The sum signal will always output the sum of a, b, and carryin.
Next, we will be combining
smaller ALUs together to form larger ALUs, first 4-bit, then 16-bit, then
finally 32-bit. This process is exactly
the same as before, with the exception that now we will use the less input of each ALU to implement a Set-on-Less-Than (SLT)
operation.
The
definition of SLT is as follows: result
= 0000…0001 if a < b, and result = 0000…0000 if a ≥
b. Note that only the least significant
bit of result changes, all other bits may be permanently assigned to 0. To accomplish this, first the binv and carryin inputs should be asserted, so that sum will output a – b. Now notice that sum will be negative (and MSB
of sum equal to 1) if and only if a <
b. So, we assign the less input of the least significant ALU
as the sum output of the most
significant ALU. As hinted at before,
all other less inputs will be
assigned to 0.
This
is the case only for the 32-bit ALU, however.
The 4-bit and 16-bit ALUs should have either a 4-bit or 16-bit less input connected to the less inputs
of the 1-bit ALUs.
Create a 4-bit ALU that is
capable of performing add/sub, bit-wise AND, and bit-wise OR instructions on
4-bit operands. The ALU should use four 1-bit ALU and a carry-look ahead module
to perform fast addition and subtraction (you may use the one designed last
semester provided that it works correctly).
Remember to include the 4-bit input less
in addition to the regular inputs. Run
simulation and make sure the 4-bit ALU works properly before moving on.
Next, using the above
module create a 16-bit ALU module. It
should use four 4-bit ALU blocks and one carry-look ahead module. Again, remember that now a 16-bit input less is needed. Run simulation and make sure the 16-bit ALU
works properly before moving on.
Finally, combine 2 16-bit
ALUs to form a 32 bit ALU. The 32-bit
ALU should set the less inputs of
the two 16-bit ALUs as described above to perform the SLT operation. For the carry, you may either use another CLA
module, or simply use ripple carry between the two 16-bit ALUs.
Run a simulation using the
vector waveform editor to verify your design and check with the TA.
6. 32-bit Shifter
The last step in this lab
is to review your design of a 32-bit shifter.
Recall that that shifter takes a 32-bit In and a 4-bit sel which
selects among the following operations:
|
an-1 |
a0 |
sel[3:0] |
Out[15:0] |
|
Left Shift |
|||
|
an-2 |
ShiftIn |
0000 |
Logic shift left with ShiftIn bit |
|
an-2 |
0 |
0001 |
Logic shift left |
|
an-2 |
an-1 |
0010 |
Rotate left |
|
an-2 |
dv |
0011 |
Divide shift left |
|
an-1 |
ShiftIn |
0100 |
Arithmetic shift left with ShiftIn bit |
|
an-1 |
0 |
0101 |
Arithmetic shift left |
|
an-1 |
a0 |
0110 |
No shift |
|
an-1 |
a0 |
0111 |
No shift |
|
Right Shift |
|||
|
an-1 |
a1 |
1000 |
Arithmetic shift right |
|
an-1 |
a1 |
1001 |
Arithmetic shift right |
|
an-1 |
a1 |
1010 |
Arithmetic shift right |
|
an-1 |
a1 |
1011 |
Arithmetic shift right |
|
ShiftIn |
a1 |
1100 |
Shift Right with ShiftIn bit |
|
0 |
a1 |
1101 |
Logic Shift Right |
|
a0 |
a1 |
1110 |
Rotate right |
|
ms |
a1 |
1111 |
Multiply shift right |
Run
a simulation to ensure that your shifter is working, then check with the TA.