CPR E 381x/382x

Initial Datapath Design

1. Objectives

In this lab you will connect the components previously designed to construct a simple datapath. For today’s lab, all testing will be done explicitly using the waveform to drive the control signals.

1.1 Reference Files for Lab

Lab Evaluation Sheet

2. Prelab

Before you come to lab make sure you have a working 32x32bit Register File, 32 bit ALU, and 32 bit shifter.

3. Setup

Create a folder in your home directory U:\CPRE381\Lab01b, and one sub-folder ~\datapath. Copy all verilog files needed for the registerfile, ALU, and shifter into this folder.

4. Datapath in Verilog

In this part, you will connect the 32x32-bit registerfile, 32-bit ALU, and 32-bit shifter together as shown below. The two outputs of the registerfile and the output of the shifter should all be sent to 32-bit registers (positive-edge triggered). The 2-1 multiplexer allows the input to the registerfile to come from either the shifter or from an input set in the waveform. All other signals (regwrite, addra, addrb, aluop, etc) should be inputs to the circuit and will be set in the waveform.

5. Testing

To test your datapath, you should set all the control signals in the waveform to perform the following operations, then simulate the circuit and make sure that it performs as expected. To observe the behavior of the datapath, make the output of the three 32-bit registers outputs in design.

Operations (all values given in decimal):

// initialize registerfile

$r0 = 0;

$r1 = 10;

$r2 = 15;

$r3 = 20;

$r4 = 25;

$r5 = 30;

$r20 = 500;

$r21 = 1500;

$r22 = 2500;

//test ALU and shifter

$r6 = $r3 + $r5;

$r25 = $r20 - $r21;

$r7 = $r6 >> 1; ($r6 shifted right logical by 1 bit)

$r30 = $r20 << 1; ($r6 shifted left logical by 1 bit)

$r8 = $r1 & $r2; (bitwise AND)

$r9 = $r21 | $r22; (bitwise OR)

$r10 = 1, if $r7 < $r5, else $r10 = 0;

$r31 = $r30 + $r10;

When you have run your simulation and are convinced that your circuit is working, have it checked by the TA.