CPR E 381x/382x - Lab 4a and 4b

Multi-Cycle CPU Implementation

1. Objectives

In this lab you will implement a multi-cycle MIPS instruction subset.

1.1 Reference Files for Lab

Lab Evaluation Form

2. Prelab

Understand the multi-cycle datapath, control unit and ALU control.

3. Setup

Create the folder in your home directory U:\CPRE381\Lab04, and then a sub-folder ~\cpu.

4. CPU in Verilog

Figure 5.28 in your Patterson & Hennessy textbook shows a multi-cycle datapath with control units. You will be implementing a similar datapath, capable of performing the subset of the full MIPS instruction set given below.

Design the control module that will generate the control signals based on the opcode of the instruction. It might be useful to construct a table that shows the value of each control signal for every instruction. For the No Op instruction, you should set the control signals such that no memory structures are written to. Be sure that your control module is working as you expect, then have it checked by the TA.

Finally, connect all modules together to form your datapath. Although there are no inputs or outputs shown in the diagram in the book, you will need to add inputs and extra multiplexers to the Memory so that it may be initialized, and some additional outputs for testing purposes.

Test the datapath with all instructions until you are convinced it is working.

OPCODES

Opcode	Instruction	Format
000000	No Op	-
000001	add	R
000010	sub	R
000011	and	R
000100	or	R
000101	slt	R
000110	lw	I
000111	sw	I
001000	beq	I
001001	bne	I
001010	addi	I
001011	andi	I
001100	ori	I
001101	slti	I
001110	j	J

Instruction Format

J Format	OPCODE	ADDRESS
	31:26	25:0

I Format	OPCODE	RS	RT	IMM/OFFSET
	31:26	25:21	20:16	15:0

R Format	OPCODE	RS	RT	RD	Unused	Unused
	31:26	25:21	20:16	15:11	10:6	5:0