CPR E 381x/382x - Lab 6 a
& b
Pipelined
CPU Implementation
1. Objectives
In this lab you will
implement a pipelined MIPS like processor.
1.1 Reference Files for Lab
2. Prelab
Understand the pipelined datapath,
control unit, forwarding, and hazard detection unit.
3. Setup
As
you did in previous labs, make sure you create the folder in your home
directory U:\CPRE381\Lab6, and then
a sub-folder ~\cpu.
4. CPU in Verilog
Figure 6.65 in your Patterson
& Hennessy textbook shows the pipelined datapath with control,
forwarding, hazard detection units. Instead
of implementing a 32-bit wide datapath processor, you are required to create a 16-bit wide CPU. Modify the datapath
accordingly to accommodate the 16-bit wide requirement and our chosen
instruction set.
Instruction Format
|
J Format |
OPCODE |
ADDRESS |
|
|
15:12 |
11:0 |
|
I/LW/SW/BEQ/BNE Format |
OPCODE |
IMM/OFFSET |
RT |
RS |
|
|
15:12 |
11:8 |
7:4 |
3:0 |
|
R Format |
OPCODE |
RD or SHIFT |
RT |
RS |
|
|
15:12 |
11:8 |
7:4 |
3:0 |
OPCODES
|
Opcode |
Instruction
Operation |
|
0000 |
add |
|
0001 |
and |
|
0010 |
or |
|
0011 |
slt |
|
0100 |
lw |
|
0101 |
sw |
|
0110 |
beq |
|
0111 |
bne |
|
1000 |
addi |
|
1001 |
andi |
|
1010 |
ori |
|
1011 |
slti |
|
1100 |
sub |
|
1101 |
shift |
|
1110 |
jr |
|
1111 |
jal |
The following is a sequence
of instructions you need to use to test your design:
0 addi r1, r0, 7 //r1=7
2 andi r5, r0, 0 //r5=0
4 add r6, r1, r1 //r6=14
loop:
6 sw r1, 6(r5) //Mem[6]=7, 2, -3
8 lw r2, -8(r6) //r2=Mem[6] = 7, 2, -3
10 and r4, r2, r5 //r4=0, 0, 0
12 or r8, r2, r6 //r8=15, 14, -1
14 add r9, r6, r2 //r9= 21, 16, 11
16 slt r7, r6, r9 //r7=1, 1, 0
18 bne r7, r0, Next
20 shift right, r9, r9 //r9>>1, r9=5
22 addi r2, r0, 2 //r2=2
Middle:
24 sub r9, r9, r2 //r9=3, 1
26 slti r14, r9, 3 //r14=0, 1
28 beq r14, r0, Middle
30 jr r15
Next:
32 addi r1, r1, -5 //r1=2, -3
34 jal loop //r15=36
36 add r0, r0, r0 //no-op
Verify with TA of your design.